View PN511_4108824.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PN511
Transmission Module
Rev. 3.3 -- 13 June 2007
082733
Product short data sheet
1. Introduction
This Product short data sheet describes the functionality of the transceiver IC PN511. It includes functional and electrical specifications. A complete specification is given in the product data sheet.
2. General description
The PN511 is a highly integrated transceiver IC for contactless communication at 13.56 MHz. This transceiver IC utilizes an outstanding modulation and demodulation concept completely integrated for different kinds of contactless communication methods and protocols at 13.56 MHz. The PN511 transceiver ICs support 3 different operating modes
* Reader/Writer mode supporting ISO 14443A/Mifare and FeliCa scheme * Card Operation mode supporting ISO 14443A/Mifare and FeliCa scheme * NFCIP-1 mode
Enabled in Reader/Writer mode for ISO 14443A/Mifare, the PN511's internal transmitter part is able to drive a reader/writer antenna designed to communicate with ISO 14443A/ Mifare cards and transponders without additional active circuitry. The receiver part provides a robust and efficient implementation of a demodulation and decoding circuitry for signals from ISO 14443A/Mifare compatible cards and transponders. The digital part handles the complete ISO 14443A framing and error detection (Parity & CRC). The PN511 supports Mifare Classic (e.g. Mifare Standard) products. The PN511 supports contactless communication using Mifare higher transfer speeds up to 424 kbit/s in both directions. Enabled in Reader/Writer mode for FeliCa, the PN511 transceiver IC supports the FeliCa communication scheme. The receiver part provides a robust and efficient implementation of the demodulation and decoding circuitry for FeliCa coded signals. The digital part handles the FeliCa framing and error detection like CRC. The PN511 supports contactless communication using FeliCa Higher transfer speeds up to 424 kbit/s in both directions. In Card Operation mode, the PN511 transceiver IC is able to answer to a reader/writer command either according to the FeliCa or ISO 14443A/Mifare card interface scheme. The PN511 generates the digital load modulated signals and in addition with an external circuit the answer can be sent back to the reader/writer. A complete card functionality is only possible in combination with a secure core IC using the S2C interface.
NXP Semiconductors
PN511
Transmission Module
Additionally, the PN511 transceiver IC offers the possibility to communicate directly to an NFCIP-1 device in the NFCIP-1 mode. The NFCIP-1 mode offers different communication mode and transfer speeds up to 424 kbit/s according to the Ecma 340 and ISO/IEC 18092 NFCIP-1 Standard. The digital part handles the complete NFCIP-1 framing and error detection. Various host controller interfaces are implemented:
* * * *
8-bit parallel interface1 SPI interface serial UART (similar to RS232 with voltage levels according pad voltage supply) I2C interface.
1.
082733
8-bit parallel Interface only available in HVQFN40 package.
(c) NXP B.V. 2007. All rights reserved.
Product short data sheet
Rev. 3.3 -- 13 June 2007
2 of 22
NXP Semiconductors
PN511
Transmission Module
3. Features
Highly integrated analog circuitry to demodulate and decode responses Buffered output drivers to connect an antenna with minimum number of external components Integrated RF Level detector Integrated data mode detector ISO 14443A/Mifare support Typical operating distance in Reader/Writer mode for communication to a ISO 14443A/ Mifare or FeliCa card up to 50 mm depending on the antenna size, tuning and power supply Typical operating distance in NFCIP-1 mode up to 50 mm depending on the antenna size and tuning and power supply Typical operating distance in ISO 14443A/Mifare card or FeliCa Card Operation mode of about 100 mm depending on the antenna size and tuning and the external field strength Mifare Classic encryption in Reader/Writer mode support ISO 14443A higher transfer speed communication at 212 kbit/s and 424 kbit/s Contactless communication according to the FeliCa scheme at 212 kbit/s and 424 kbit/s Integrated RF interface for NFCIP-1 up to 424 kbit/s S2C interface Supported host controller interfaces SPI interface up to 10 Mbit/s I2C interface up to 400 kbit/s in Fast mode, up to 3400 kbit/s in High-speed mode serial UART in different transfer speeds up to 1228.8 kbit/s, framing according to the RS232 interface with voltage levels according pad voltage supply 8-bit parallel interface with and without Address Latch Enable Comfortable 64 byte send and receive FIFO-buffer Flexible interrupt modes Hard reset with low power function Power-down mode per software Programmable timer Internal oscillator to connect 27.12 MHz quartz 2.5-3.6 V power supply CRC Co-processor Free programmable I/O pins Internal self test
082733
(c) NXP B.V. 2007. All rights reserved.
Product short data sheet
Rev. 3.3 -- 13 June 2007
3 of 22
NXP Semiconductors
PN511
Transmission Module
4. Quick reference data
Table 1. Symbol AVDD DVDD TVDD PVDD IHPD Hard Power-down Current AVDD = DVDD = TVDD = PVDD = 3 V, NRESET = LOW AVDD = DVDD = TVDD = PVDD = 3 V, RF level detector on DVDD = 3 V AVDD = 3 V, bit RCVOff = 0 AVDD = 3 V, bit RCVOff = 1
[5]
Quick reference data Parameter Supply Voltage Conditions AVSS = DVSS = PVSS= TVSS = 0 V, PVDD AVDD = DVDD =TVDD
[1][2] [1][2] [1][2] [3] [7]
Min 2.5
Typ -
Max 3.6
Unit V
1.6 -
-
3.6 5
V A
ISPD IDVDD IAVDD IAVDD,RCVOFF IPVDD ITVDD Tamb
[1] [2] [3] [4] [5] [6] [7] [8]
Soft Power-down Current Digital Supply Current Analog Supply Current Analog Supply Current, receiver switched off Pad Supply Current Transmitter Supply Current operating ambient temperature
[7]
-30
6.5 7 3 60
10 9 10 5 40 100 +85
A mA mA mA mA mA C
Continuous Wave
[4][6][8]
Supply voltage below 3 V reduces the performance (e.g. the achievable operating distance). AVDD, DVDD and TVDD shall always be on the same voltage level. PVDD shall always be on the same or lower voltage level than DVDD. ITVDD depends on TVDD and the external circuitry connected to Tx1 and Tx2 IPVDD depends on the overall load at the digital pins. During operation with a typical circuitry the overall current is below 100 mA. ISPD and IHPD are the total currents over all supplies. Typical value using a complementary driver configuration and an antenna matched to 40 between TX1 and TX2 at 13.56 MHz
5. Ordering information
Table 2. Ordering information Package Name PN5110A0HN1/C2 PN5110A0HN/C2 HVQFN32 HVQFN40 Description Plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm Plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6x 6x 0.85 mm Version SOT617 SOT618 Type number
082733
(c) NXP B.V. 2007. All rights reserved.
Product short data sheet
Rev. 3.3 -- 13 June 2007
4 of 22
NXP Semiconductors
PN511
Transmission Module
6. Block diagram
The Analog interface handles the modulation and demodulation of the analog signals according to the Card Receiving mode, Reader/Writer mode and NFCIP-1 mode communication scheme. The RF level detector detects the presence of an external RF-field delivered by the antenna to the RX pin. The Data mode detector detects a Mifare, FeliCa or NFCIP-1 mode in order to prepare the internal receiver to demodulate signals, which are sent to the PN511. The communication (S2C) interface provides digital signals to support communication for transfer speeds above 424 kbit/s and digital signals to communicate to a secure smart card IC.
082733
(c) NXP B.V. 2007. All rights reserved.
Product short data sheet
Rev. 3.3 -- 13 June 2007
5 of 22
NXP Semiconductors
PN511
Transmission Module
NWR NRD
NCS
ALE
A0 to A5
D0 to D7 PVDD PVSS
DVDD
8 bit Parallel, SPI, UART, I2C Interface Control
(incl. Automatic Interface Detection & Synchronisation)
Voltage Monitor & Power On Detect State Machine Reset Control
DVSS
AVDD AVSS
FIFO Control
Command Register 64 Byte FIFO
Programable Timer
Power Down Control
NRSTPD
Control Register Bank Interrupt Control
IRQ
CRC16 Generation & Check MIFARE Classic Unit
Parallel/Seriell Converter Random Number Generator Bit Counter
Parity Generation & Check
Frame Generation & Check
Bit Decoding
Bit Coding
Card Mode Detector
SIGIN
Serial Data Switch
SIGOUT LOADMOD
Amplitude Rating A/D Converter Reference Voltage
Clock Generation, Filtering and Distribution
OSCIN
Oscillator
OSCOUT
Q-Clock Generation Analog Test MUX and DAC I-Channel Amplifier I-Channel Demodulator Q-Channel Amplifier Q-Channel Demodulator RF clock recovery RF Level Detector
G ND V+
Temperature Sensor
Transmitter Control
G ND
V+
VMID
AUX1,2
RX TVSS TX1 TX2 TVDD
Fig 1. PN511 Block diagram
082733 (c) NXP B.V. 2007. All rights reserved.
Product short data sheet
Rev. 3.3 -- 13 June 2007
6 of 22
NXP Semiconductors
PN511
Transmission Module
7. Pinning information
7.1 Pinning
31 D7
30 D6
29 D5
28 D4
27 D3
26 D2
A1 PVDD DVDD DVSS PVSS NRSTPD SIGIN SIGOUT
1 2 3 4 5 6 7 8 TVSS 10 TX1 11 TVDD 12 TX2 13 TVSS 14 AVDD 15 VMID 16 32 D1 9
25 D1 24 ALE 23 IRQ 22 OSCOUT 21 OSCIN 20 AUX2 19 AUX1 18 AVSS 17 RX
SOT617-1
32 A0
terminal 1 index area
PN511
LOADMOD terminal 1 index area A2 A3 A4 A5 PVDD DVDD DVSS PVSS NRSTPD 1 2 3 4 5 6 7 8 9
Transparent top view
Fig 2. Pinning configuration HVQFN32 (SOT617-1)
38 D7
37 D6
36 D5
35 D4
34 D3
33 D2
31 D0 30 NCS 29 ALE 28 NRD 27 NWR 26 IRQ 25 OSCOUT 24 OSCIN 23 AUX2 22 AUX1 21 AVSS RX 20
SOT618-1
40 A1
39 A0
PN511
SIGIN 10 SIGOUT 11 LOADMOD 12 TVSS 13 TX1 14 TVDD 15 TX2 16 TVSS 17 AVDD 18 VMID 19
Transparent top view
Fig 3. Pinning configuration HVQFN40 (SOT618)
082733
(c) NXP B.V. 2007. All rights reserved.
Product short data sheet
Rev. 3.3 -- 13 June 2007
7 of 22
NXP Semiconductors
PN511
Transmission Module
7.2 Pin description
Table 3. Symbol A1 PVDD DVDD DVSS PVSS NRSTPD Pin description HVQFN32 Pin 1 2 3 4 5 6 Type I PWR PWR PWR PWR I Description Address Line Pad power supply Digital Power Supply Digital Ground Pad power supply ground Not Reset and Power Down: When LOW, internal current sinks are switched off, the oscillator is inhibited, and the input pads are disconnected from the outside world. With a positive edge on this pin the internal reset phase starts. Communication Interface Input: accepts a digital, serial data stream Communication Interface Output: delivers a serial data stream Load Modulation Output: provides digital signal for FeliCa and Mifare Card Operation mode Transmitter Ground: supplies the output stage of TX1 and TX2 Transmitter 1: delivers the modulated 13.56 MHz energy carrier Transmitter Power Supply: supplies the output stage of TX1 and TX2 Transmitter 2: delivers the modulated 13.56 MHz energy carrier Transmitter Ground: supplies the output stage of TX1 and TX2 Analog Power Supply Internal Reference Voltage: This pin delivers the internal reference voltage. Receiver Input Analog Ground Auxiliary Outputs: These pins are used for testing. Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin is also the input for an externally generated clock (fosc = 27.12 MHz). Crystal Oscillator Output: Output of the inverting amplifier of the oscillator. Interrupt Request: output to signal an interrupt event Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch when HIGH. 8-bit Bi-directional Data Bus. Remark: An 8-bit parallel interface is not available. Remark: If the host controller selects I2C as digital host controller interface, these pins can be used to define the I2C address. Remark: For serial interfaces this pins can be used for test signals or I/Os. A0 32 I Address Line
SIGIN SIGOUT LOADMOD TVSS TX1 TVDD TX2 TVSS AVDD VMID RX AVSS AUX1 AUX2 OSCIN OSCOUT IRQ ALE D1 to D7
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 to 31
I O O PWR O PWR O PWR PWR PWR I PWR O O I O O I I/O
082733
(c) NXP B.V. 2007. All rights reserved.
Product short data sheet
Rev. 3.3 -- 13 June 2007
8 of 22
NXP Semiconductors
PN511
Transmission Module
Table 4. Symbol A2 to A5 PVDD DVDD DVSS PVSS NRSTPD
Pin description HVQFN40 Pin 1 to 4 5 6 7 8 9 Type I PWR PWR PWR PWR I Description Address Line Pad power supply Digital Power Supply Digital Ground Pad power supply ground Not Reset and Power Down: When LOW, internal current sinks are switched off, the oscillator is inhibited, and the input pads are disconnected from the outside world. With a positive edge on this pin the internal reset phase starts. Communication Interface Input: accepts a digital, serial data stream Communication Interface Output: delivers a serial data stream Load Modulation Output: provides digital signal for FeliCa and Mifare Card Operation mode Transmitter Ground: supplies the output stage of TX1 and TX2 Transmitter 1: delivers the modulated 13.56 MHz energy carrier Transmitter Power Supply: supplies the output stage of TX1 and TX2 Transmitter 2: delivers the modulated 13.56 MHz energy carrier Transmitter Ground: supplies the output stage of TX1 and TX2 Analog Power Supply Internal Reference Voltage: This pin delivers the internal reference voltage. Receiver Input Analog Ground Auxiliary Outputs: These pins are used for testing. Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin is also the input for an externally generated clock (fosc = 27.12 MHz). Crystal Oscillator Output: Output of the inverting amplifier of the oscillator. Interrupt Request: output to signal an interrupt event Not Write: strobe to write data (applied on D0 to D7) into the PN511 register Not Read: strobe to read data from the PN511 register (applied on D0 to D7) Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch when HIGH. Not Chip Select: selects and activates the host controller interface of the PN511 8-bit Bi-directional Data Bus. Remark: For serial interfaces this pins can be used for test signals or I/Os. Remark: If the host controller selects I2C as digital host controller interface, these pins can be used to define the I2C address.
SIGIN SIGOUT LOADMOD TVSS TX1 TVDD TX2 TVSS AVDD VMID RX AVSS AUX1 AUX2 OSCIN OSCOUT IRQ NWR NRD ALE NCS D0 to D7
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 to 38
I O O PWR O PWR O PWR PWR PWR I PWR O O I O O I I I I I/O
A0 to1 A1
39 to 40
I
Address Line
082733
(c) NXP B.V. 2007. All rights reserved.
Product short data sheet
Rev. 3.3 -- 13 June 2007
9 of 22
NXP Semiconductors
PN511
Transmission Module
8. Operating modes
PN511 transceiver IC supports the following operating modes:
* Reader/Writer mode supporting ISO 14443A/Mifare and FeliCa scheme * Card Operation mode supporting ISO 14443A/ Mifare and FeliCa scheme * NFCIP-1 mode
The modes support different transfer speeds and modulation schemes. The following chapters will explain the different modes in detail. Note: All indicated modulation indices and modes in this chapter are system parameters. This means that beside the IC settings a suitable antenna tuning is required to achieve the optimum performance.
8.1 Reader/Writer mode
Generally 2 Reader/Writer modes are supported. The PN511 can act as a reader/writer for ISO 14443A/Mifare or FeliCa cards.
Battery PN511
C
Reader / Writer
Fig 4. Reader/Writer mode
ISO14443A or FeliCa Card Contactless Card
In the Reader/Writer mode the PN511 enables the communication to a contactless ISO 14443A/Mifare or FeliCa card.
8.1.1 ISO 14443A/Mifare reader/writer functionality
The ISO 14443A/Mifare Reader/Writer mode is the general reader to card communication scheme according to the ISO 14443A/Mifare specification.The following diagram describes the communication on a physical level, the communication table describes the physical parameters.
ISO14443A Reader (PCD)
1. PCD to PICC 100 % ASK , Miller Coded, baudrate 106 to 424 kbaud
ISO14443A Card (PICC)
PN511 2. PICC to PCD, Subcarrier Loadmodulation, Manchester Coded or BPSK, baudrate 106 to 424 kbaud
Fig 5.
082733
ISO 14443A/Mifare Reader/Writer mode communication diagram
(c) NXP B.V. 2007. All rights reserved.
Product short data sheet
Rev. 3.3 -- 13 June 2007
10 of 22
NXP Semiconductors
PN511
Transmission Module
Communication overview for ISO 14443A/Mifare reader/writer ISO 14443A/Mifare 106 kbit/s 100% ASK Modified Miller coding (128/13.56) s subcarrier load modulation 13.56 MHz/16 Manchester coding Mifare Higher transfer speeds 212 kbit/s 100% ASK Modified Miller coding (64/13.56) s subcarrier load modulation 13.56 MHz/16 BPSK 424 kbit/s 100% ASK Modified Miller coding (32/13.56) s subcarrier load modulation 13.56 MHz/16 BPSK
Table 5.
Communication direction transfer speed PN511 PICC (send data from the PN511 to a card) Modulation on reader side bit coding Bitlength PICC PN511 (receive data from a card) modulation on card side subcarrier frequency bit coding
The contactless UART of PN511 and a dedicated external host controller are required to handle the complete Mifare/ISO 14443A/Mifare protocol. 8.1.1.1 Data Coding and framing according to ISO 14443A/Mifare The internal CRC co-processor calculates the CRC value according to the definitions given in the ISO 14443A part 3 and handles parity generation internally according to the transfer speed.
Current ISO14443 Framing for Type A for 106 kBaud
Start
8 bit data
odd Par.
8 bit data
odd Par.
8 bit data
odd Par.
Start Bit is "1"
MIFARE Higher Baudrate Framing for 212, 424 kBaud
Start
8 bit data
odd Par.
8 bit data
odd Par.
8 bit data
even Par.
Start Bit is "0" Burst of 32 sub-carrier clocks
Even parity at the end of the frame!
Fig 6.
Data Coding and framing according to ISO 14443A
082733
(c) NXP B.V. 2007. All rights reserved.
Product short data sheet
Rev. 3.3 -- 13 June 2007
11 of 22
NXP Semiconductors
PN511
Transmission Module
8.1.2 FeliCa reader/writer functionality
The FeliCa mode is the general reader/writer to card communication scheme according to the FeliCa specification. The following diagram describes the communication on a physical level, the communication overview describes the physical parameters.
FeliCa Reader (PCD) PN511
1. PCD to PICC 8-30 % ASK M , anchester Coded, baudrate 212 to 424 kbaud
FeliCa Card (PICC)
2. PICC to PCD, >12 % ASK Loadmodulation , Manchester Coded, baudrate 212 to 424 kbaud
Fig 7. Table 6.
FeliCa reader/writer Communication Diagram Communication overview for FeliCa reader/writer FeliCa Transfer speed 212 kbit/s 8-30% ASK Manchester Coding (64/13.56) s >12% ASK Manchester coding FeliCa Higher transfer speeds 424 kbit/s 8-30% ASK Manchester Coding (32/13.56) s >12% ASK Manchester coding
Communication direction PN511 card Modulation on reader side bit coding Bitlength card PN511 Loadmodulation on card side bit coding
The contactless UART of PN511 and a dedicated external host controller are required to handle the complete FeliCa protocol. 8.1.2.1 FeliCa framing and coding
Table 7. 00h 00h FeliCa framing and coding Preamble 00h 00h 00h 00h Sync B2h 4Dh Len n-Data CRC
To enable the FeliCa communication a 6 byte preamble (00h, 00h, 00h, 00h, 00h, 00h) and 2 bytes Sync bytes (B2h, 4Dh) are sent to synchronize the receiver. The following Len byte indicates the length of the sent data bytes plus the LEN byte itself. The CRC calculation is done according to the FeliCa definitions with the MSB first. To transmit data on the RF interface, the host controller has to send the Len- and databytes to the PN511's FIFO buffer. The preamble and the sync bytes are generated by the PN511 automatically and must not be written to the FIFO by the host controller. The PN511 performs internally the CRC calculation and adds the result to the data frame. Example for FeliCa CRC Calculation:
Table 8. 00h
082733
Start Value for the CRC Polynomial: (00h), (00h) Preamble 00h 00h 00h 00h 00h Sync B2h 4Dh Len 03h 2 Data Bytes ABh CDh CRC 90h 35h
(c) NXP B.V. 2007. All rights reserved.
Product short data sheet
Rev. 3.3 -- 13 June 2007
12 of 22
NXP Semiconductors
PN511
Transmission Module
8.2 NFCIP-1 mode
The NFCIP-1 communication differentiates between an active and a Passive Communication mode.
* Active Communication mode means both the initiator and the target are using their
own RF field to transmit data.
* Passive Communication mode means that the target answers to an initiator command
in a load modulation scheme. The initiator is active in terms of generating the RF field.
* Initiator: generates RF field at 13.56 MHz and starts the NFCIP-1 communication * Target: responds to initiator command either in a load modulation scheme in Passive
Communication mode or using a self generated and self modulated RF field for Active Communication mode. In order to fully support the NFCIP-1 standard the PN511 supports the Active and Passive Communication mode at the transfer speeds 106 kbit/s, 212 kbit/s and 424 kbit/s as defined in the NFCIP-1 standard.
Battery PN511 PN511
C Battery Target: Passive or Active
C
Initiator:Active
Fig 8. NFCIP-1 mode
082733
(c) NXP B.V. 2007. All rights reserved.
Product short data sheet
Rev. 3.3 -- 13 June 2007
13 of 22
NXP Semiconductors
PN511
Transmission Module
8.2.1 Active Communication mode
Active Communication mode means both the initiator and the target are using their own RF field to transmit data.
Initial Command
Host Host NFC Initiator NFC Target
1. Initiator starts communication at selected transfer speed Response
powered for digital processing
powered to generate RF field
Host NFC Initiator
NFC Target
Host
2. Target answers at the same transfer speed
powered for digital processing
Fig 9. Active Communication mode Table 9. Communication Overview for Active Communication mode 212 kbit/s 424 kbit/s 848 kbit/s 1.69 Mbit/s, 3.39 Mbit/s
powered to generate RF field
Communication 106 kbit/s direction Initiator Target According to Target Initiator ISO 14443A 100% ASK, Modified Miller Coded
According to FeliCa, 8-30% digital capability to handle ASK Manchester Coded this communication
The contactless UART of PN511 and a dedicated host controller are required to handle the NFCIP-1 protocol. Note: Transfer Speeds above 424 kbit/s are not defined in the NFCIP-1 standard. The PN511 supports these transfer speeds only with dedicated external circuits.
082733
(c) NXP B.V. 2007. All rights reserved.
Product short data sheet
Rev. 3.3 -- 13 June 2007
14 of 22
NXP Semiconductors
PN511
Transmission Module
8.2.2 Passive Communication mode
Passive Communication mode means that the target answers to an initiator command in a load modulation scheme. The initiator is active meaning generating the RF field.
Fig 10. Passive Communication mode Table 10. Communication Overview for Passive Communication mode 212 kbit/s 424 kbit/s 848 kbit/s 1.69 Mbit/s, 3.39 Mbit/s
Communication 106 kbit/s direction Initiator Target According to ISO 14443A 100% ASK, Modified Miller Coded
According to FeliCa, 8-30% digital capability to handle ASK Manchester Coded this communication
Target Initiator According to According to FeliCa, >12% ISO 14443A ASK Manchester Coded subcarrier load modulation, Manchester Coded
The contactless UART of PN511 and a dedicated host controller are required to handle the NFCIP-1 protocol. Note: Transfer Speeds above 424 kbit/s are not defined in the NFCIP-1 standard. The PN511 supports these transfer speeds only with dedicated external circuits.
082733
(c) NXP B.V. 2007. All rights reserved.
Product short data sheet
Rev. 3.3 -- 13 June 2007
15 of 22
NXP Semiconductors
PN511
Transmission Module
8.2.3 NFCIP-1 framing and coding
The NFCIP-1 framing and coding in Active and Passive Communication mode is defined in the NFCIP-1 standard.
Table 11. 106 kbit/s 212 kbit/s 424 kbit/s Framing and Coding Overview Framing and Coding According to the ISO 14443A/Mifare scheme According to the FeliCa scheme According to the FeliCa scheme
Transfer speed
8.2.4 NFCIP-1 Protocol Support
The NFCIP-1 protocol is not completely described in this document. For detailed explanation of the protocol refer to the NFCIP-1 standard. However the datalink layer is according to the following policy:
* Speed shall not be changed while continuum data exchange in a transaction. * Transaction includes initialization and anticollision methods and data exchange (in
continuous way, meaning no interruption by another transaction). In order not to disturb current infrastructure based on 13.56 MHz general rules to start NFCIP-1 communication are defined in the following way. 1. Per default NFCIP-1 device is in Target mode meaning its RF field is switched off. 2. The RF level detector is active. 3. Only if application requires the NFCIP-1 device shall switch to Initiator mode. 4. Initiator shall only switch on its RF field if no external RF field is detected by RF Level detector during a time of TIDT. 5. The initiator performs initialization according to the selected mode.
8.3 Card Operation mode
The PN511 can be addressed like a FeliCa or ISO 14443A/Mifare card. This means that the PN511 can generate an answer in a load modulation scheme according to the ISO 14443A/Mifare or FeliCa interface description. Note: The PN511 does not support a complete card protocol. This has to be handled by a dedicated card SAM or a host controller. The card-SAM is optional.
Reader/ Writer for FeliCa or MIFARE
PN511
C and Sam (opt.) Battery
Generates RF field
Fig 11. Card Operation mode
082733
Answers in Loadmodulation scheme
(c) NXP B.V. 2007. All rights reserved.
Product short data sheet
Rev. 3.3 -- 13 June 2007
16 of 22
NXP Semiconductors
PN511
Transmission Module
8.3.1 Mifare Card Operation mode
Table 12. Mifare Card Operation mode Mifare Higher transfer speeds 212 kbit/s 100% ASK Modified Miller (64/13.56) s subcarrier load modulation 13.56 MHz/16 BPSK 424 kbit/s 100% ASK Modified Miller (32/13.56) s subcarrier load modulation 13.56 MHz/16 BPSK Communication ISO 14443A/Mifare direction Transfer speed 106 kbit/s reader / writer Modulation on PN511 reader side bit coding Bitlength PN511 reader/ Modulation on writer PN511 side subcarrier frequency bit coding 100% ASK Modified Miller (128/13.56) s subcarrier load modulation 13.56 MHz/16 Manchester coding
8.3.2 FeliCa Card Operation mode
FeliCa Card Operation mode Communication direction Transfer speed reader/writer PN511 Modulation on reader side bit coding Bitlength PN511 reader/ Load modulation on PN511 writer side bit coding FeliCa 212 kbit/s 8-30% ASK Manchester Coding (64/13.56) s >12% ASK load modulation Manchester coding FeliCa Higher transfer speeds 424 kbit/s 8-30% ASK Manchester Coding (32/13.56) s >12% ASK load modulation Manchester coding
082733
(c) NXP B.V. 2007. All rights reserved.
Product short data sheet
Rev. 3.3 -- 13 June 2007
17 of 22
NXP Semiconductors
PN511
Transmission Module
9. Application design-in information
The figure below shows a typical circuit diagram, using a complementary antenna connection to the PN511. The antenna tuning and RF part matching is described in the application note PN511 transceiver IC; Antenna and RF Design Guide
supply
DVDD PVDD
AVDD
TVDD RX R1 VMID
CRx
PVSS NRSTPD TX1
Cvmid L0 C0 TVSS C0
R2
C1 C2
RQ
Host Controller
Interface
PN511
Antenna C2 C1 RQ
IRQ
IRQ AVSS OSCIN
TX2 L0 DVSS OSCOUT
27,12 MHz
Fig 12. Typical Circuit Diagram
082733
(c) NXP B.V. 2007. All rights reserved.
Product short data sheet
Rev. 3.3 -- 13 June 2007
18 of 22
NXP Semiconductors
PN511
Transmission Module
10. Limiting values
Table 13. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol PVDD Ptot TJ ESDH ESDM ESDC Parameter Supply voltage Total power dissipation per package (VBUS and DVDD in short cut mode) Junction temperature range ESD Susceptibility (Human Body model) ESD Susceptibility (Machine model) ESD Susceptibility (Charge Device model) 1500 , 100 pF; JESD22-A114-B 0.75 H, 200 pF; JESD22-A114-A Field induced model; JESC22-C101-A Conditions Min -0.5 Max +4.0 200 100 2000 200 1000 Unit V mW C V V V
11. Package information
The PN511 can be delivered in 2 different packages.
Table 14. Package HVQFN32 HVQFN40 Package Information Remarks 8-bit parallel interface not supported Supports the 8-bit parallel interface
12. Abbreviations
Table 15. Acronym ASK Initiator Loadmodulation Index Modulation Index PCD PICC PCD PICC PICC PCD SAM Target Abbreviations Description Amplitude Shift keying Generates RF field at 13.56 MHz and starts the NFCIP-1 communication. The load modulation index is defined as the card's voltage ratio (Vmax - Vmin)/ (Vmax + Vmin) measured at the card's coil. The modulation index is defined as the voltage ratio (Vmax - Vmin)/ (Vmax + Vmin). Proximity Coupling Device. Definition for a Card reader/writer according to the ISO 14443 specification. Proximity Cards. Definition for a contactless Smart Card according to the ISO 14443 specification. Communication flow between a PCD and a PICC according to the ISO 14443A/Mifare. Communication flow between a PICC and a PCD according to the ISO 14443A/Mifare. Secure Access Module Responds to initiator command either using load modulation scheme (RF field generated by Initiator) or using modulation of self generated RF field (no RF field generated by initiator).
082733
(c) NXP B.V. 2007. All rights reserved.
Product short data sheet
Rev. 3.3 -- 13 June 2007
19 of 22
NXP Semiconductors
PN511
Transmission Module
13. Revision history
Table 16. 082733 Modifications: 082732 Modifications: Revision history Release date Juni 2007 Data sheet status Product short data sheet Product short data sheet Change notice Supersedes Revision 3.2 Revision 3.1 Document ID
* * * * * *
Add Section 14.4 "Licenses" Usage of expression "host controller" unified Order information "Type number" in Table 2 on page 4 updated from PN5110A0HN1/C1 to PN5110A0HN1/C2 Product short data sheet Revision 3.0 The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 7.2 "Pin description" on page 8: - corrected in Table 3 "Pin description HVQFN32" Type of Pin 12: 0 -> PWR - corrected in Table 4 "Pin description HVQFN40" on page 9 Type of Pin 15: 0 -> PWR
Januar 2007
082731 Modifications:
16 October 2006
*
082730 082720 082710
Section 8.1.2 "FeliCa reader/writer functionality" on page 12: - Table 6 "Communication overview for FeliCa reader/writer" renamed Table Title Product short data sheet Preliminary short data sheet Objective short data sheet Revision 2.0 Revision 1.0 -
7 July 2006 1 February 2004 1 March 2003
082733
(c) NXP B.V. 2007. All rights reserved.
Product short data sheet
Rev. 3.3 -- 13 June 2007
20 of 22
NXP Semiconductors
PN511
Transmission Module
14. Legal information
14.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
14.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk.
14.4 Licenses
Purchase of an NXP Semiconductors IC that complies with one of the NFC Standards (ISO/IEC18.092; ISO/IEC21.481) does not convey an implied license under any patent right on that standards.
Purchase of an NXP Semiconductors IC that complies with one of the NFC Standards (ISO/IEC18.092; ISO/IEC21.481) does not convey an implied license under any patent right on that standards. A license for the portfolio of the NFC Standards patents of NXP B.V. needs to be obtained at Via Licensing, the pool agent of the NFC Patent Pool, e-mail: info@vialicensing.com
14.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Mifare -- is a trademark of NXP B.V.
15. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
082733
(c) NXP B.V. 2007. All rights reserved.
Product short data sheet
Rev. 3.3 -- 13 June 2007
21 of 22
NXP Semiconductors
PN511
Transmission Module
16. Tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Quick reference data . . . . . . . . . . . . . . . . . . . . .4 Ordering information . . . . . . . . . . . . . . . . . . . . .4 Pin description HVQFN32 . . . . . . . . . . . . . . . . .8 Pin description HVQFN40 . . . . . . . . . . . . . . . . .9 Communication overview for ISO 14443A/Mifare reader/writer . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Communication overview for FeliCa reader/writer . . . . . . . . . . . . . . . . . . . . . . . . . . .12 FeliCa framing and coding . . . . . . . . . . . . . . . .12 Start Value for the CRC Polynomial: (00h), (00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Communication Overview for Active Communication mode . . . . . . . . . . . . . . . . . . . 14 Communication Overview for Passive Communication mode . . . . . . . . . . . . . . . . . . . 15 Framing and Coding Overview . . . . . . . . . . . . 16 Mifare Card Operation mode . . . . . . . . . . . . . . 17 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 19 Package Information . . . . . . . . . . . . . . . . . . . . 19 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20
17. Figures
Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. PN511 Block diagram . . . . . . . . . . . . . . . . . . . . . .6 Pinning configuration HVQFN32 (SOT617-1) . . . .7 Pinning configuration HVQFN40 (SOT618) . . . . . .7 Reader/Writer mode. . . . . . . . . . . . . . . . . . . . . . .10 ISO 14443A/Mifare Reader/Writer mode communication diagram. . . . . . . . . . . . . . . . . . . .10 Fig 6. Data Coding and framing according to ISO 14443A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Fig 7. FeliCa reader/writer Communication Diagram . . 12 Fig 8. NFCIP-1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Fig 9. Active Communication mode . . . . . . . . . . . . . . . 14 Fig 10. Passive Communication mode . . . . . . . . . . . . . . 15 Fig 11. Card Operation mode . . . . . . . . . . . . . . . . . . . . . 16 Fig 12. Typical Circuit Diagram . . . . . . . . . . . . . . . . . . . . 18
18. Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Quick reference data . . . . . . . . . . . . . . . . . . . . . 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 7 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 Operating modes . . . . . . . . . . . . . . . . . . . . . . . 10 Reader/Writer mode . . . . . . . . . . . . . . . . . . . . 10 ISO 14443A/Mifare reader/writer functionality 10 Data Coding and framing according to ISO 14443A/Mifare . . . . . . . . . . . . . . . . . . . . . 11 8.1.2 FeliCa reader/writer functionality . . . . . . . . . . 12 8.1.2.1 FeliCa framing and coding . . . . . . . . . . . . . . . 12 8.2 NFCIP-1 mode . . . . . . . . . . . . . . . . . . . . . . . . 13 8.2.1 Active Communication mode . . . . . . . . . . . . . 14 8.2.2 Passive Communication mode . . . . . . . . . . . . 15 8.2.3 NFCIP-1 framing and coding . . . . . . . . . . . . . 16 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.1.1 8.1.1.1 8.2.4 8.3 8.3.1 8.3.2 9 10 11 12 13 14 14.1 14.2 14.3 14.4 14.5 15 16 17 18 NFCIP-1 Protocol Support . . . . . . . . . . . . . . . Card Operation mode . . . . . . . . . . . . . . . . . . Mifare Card Operation mode . . . . . . . . . . . . . FeliCa Card Operation mode . . . . . . . . . . . . . Application design-in information . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Package information. . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 17 17 18 19 19 19 20 21 21 21 21 21 21 21 22 22 22
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 13 June 2007 Document identifier: 082733

▲Up To Search▲

Price & Availability of PN511

	To Download PN511 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .